CSE 240B -- Advanced Computer Architecture

Spring 2005, Instructor: Dean Tullsen

Announcements:

Homework assignments

Basic Course Information:

Instructor: Dean Tullsen

AP&M 4250
tullsen at cs

office hours: Tu Th 3:30-4:30

Meeting times

TuTh 2:00-3:20, HSS 2154

Course textbook

Patterson & Hennessy, "Computer Architecture: A Quantitative Approach", Morgan Kaufmann, Third Edition
Hill, Jouppi, Sohi, "Readings in Computer Architecture", Morgan Kaufmann
these will be supplemented with other readings during the course. Stay tuned.

Other recommended reading

"Parallel Computer Architecture: A Hardware/Software Approach," Culler, Singh, Gupta, Morgan Kaufmann.
WWW Computer Architecture Home Page

a comprehensive guide to research and general information on computer architecture available on the web.

Assignments will be quite varied. Examples of things you may be asked to do in this class:

problem sets
paper summaries -- a paper summary is no more than 1 page long (no more than 2 pages total for all papers for a particular day), and contains the following information: (1) summary of the paper [in the neighborhood of 2-3 sentences, everything else about 1 sentence each], (2) What is the most important result?, (3) One strength of the paper, (4) one weakness of the paper, (5) one thing you didn't understand, (6) if you wrote this paper, what would your next paper be about?
mini-project -- this could be either an easy programming project or an easy simulation project.
project -- this is a unique piece of work, done in groups of 1-3, of high depth and quality.

Grades will be determined something like this:

homework, paper summaries, mini-projects 10-20%
project 30%
midterm 20%
final 30%
class participation 10%

Class will be a combination of lecture and guided discussion. Make sure you come prepared for the latter. If not, I will bump up the portion of the grade for class participation until I am happy with the level of discussion.
A class mailing list will be set up. Make sure you're on it.

Course Outline:

I. Parallel Computer Architecture

cache coherence protocols
synchronization
consistency models
case studies
chip multiprocessors

II. Historical Architectures

III. Instruction Level Parallelism

branch prediction
ILP limits
predicated execution
dynamic scheduling
case studies

IV. Cache/Memory Hierarchy

VI. Other Interesting Architectures

dataflow machines
multithreading
trace processors
speculative threading

Lecture slides: MP1, MP2, MP3, SMT

Class	Readings (Very approximate, at this point!)
March 29	Introduction
March 31	H&P 6.1, 6.3, 6.4, 6.5
April 5	H&P 6.6-6.8
April 7	Finish memory consistency, plus: The DASH Prototype: Logic Overhead and Performance.
April 12	Memory Coherence in Shared Virtual Memory Systems An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors
April 14	Architecture and Applications of the HEP multiprocessor computing system, The Tera Computer System, Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
April 19	(1) The Case for a Single-Chip Multiprocessor (2) Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture (3) Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance background, not required: Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
April 21	(1)Architecture of the IBM System/360 (2) Parallel Operation in the Control Data 6600 (3) The CRAY-1 Computer System (4) CRAY-1 Computer Technology also read pages 1-16 of the text (pages 1-55 in total)
April 26	(1) Cramming More Components onto Integrated Circuits, (2) Two-Level Adaptive Training Branch Prediction (3) The YAGS branch prediction scheme
April 28	(1) Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor (2) Neural Methods for Dynamic Branch Prediction
May 3	(1) A Comparison of Full and Partial Predicated Execution Support for ILP Processors (2) Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors (3) Highly accurate data value prediction using hybrid predictors
May 5	(1) Multiscalar Processors (2) A Scalable Approach to Thread-Level Speculation (3) A Quantitative Assessment of Thread-Level Speculation Techniques
May 10	midterm
May 12	(1) Execution-based Prediction Using Speculative Slices (2) Dynamic Speculative Precomputation
May 17	(1) Mitosis Compiler: An Infrastructure for Speculative Threading Based on Pre-Computation Slices (2) Threaded Multi-path Execution
May 19	(1) The Alpha 21264 Microprocessor (2) The Microarchitecture of the Pentium 4 Processor
May 24	(1) Improving Direct-Mapped Cache ... (Jouppi) (2) Organization and Performance of a Two-Level ... (Wang, Baer, Levy)
May 26	(1) Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching (2) Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
May 31	(1) Opportunistic Transient-Fault Detection (2) Design and Evaluation of Hybrid Fault-Detection Systems<
June 2	Final
June 9	Project Presentations 1-4 p.m., APM 4218