CSE 140L Spring 2008: Announcements | Syllabus | Schedule | Materials

---

CSE 140L Spring 2008

Schedule

---

This schedule is tentative, and subject to change. Lab report is due at the beginning of class. Late report will not be graded and you will receive 0pts for that particular lab assignment.

Date	Lecture Topic	Reading	Lab assignment
W 04/02	Introduction	Ch. 1, 9.4, B.1, B.4-7	Lab 1 out Due date: Apr. 23
W 04/09	Timing, Mux, Demux, Adders	Ch. 3.5, 4.2, 5.6
W 04/16	Verilog	Ch. 3.6, Verilog handout
W 04/23	Verilog and FFs	Ch. 6, App. C	Lab 2 out Due date: May. 07 Solutions
W 04/30	FFs and FSMs	Ch. 6, Ch. 7
W 05/07	FSMs and Verilog	Ch. 7, 8	Lab 3 out Due date: May. 21 Solutions
W 05/14	FSMs and implementations	Ch. 8, 9
W 05/21	Memory and PLDs	Ch. 9, 10	Lab 4 out Due date: June 4 Solutions
W 05/28	CPU design	Ch. 1-10
W 06/04	RTL synthesis and review	Ch. 1-10, RTL handout
Finals Week
F 06/13	FINAL EXAM: 3:00pm-6:00pm