CSE 140L Digital Design Systems Labs Spring 2009

University of California, San Diego

Course Information

Objective of this course is to introduce digital components and provide hands-on experience in building digital circuits using computer aided design software. Altera Quartus II program is the primary software tool: https://www.altera.com/.

Instructor

• CK Cheng, CSE2130, ckcheng+140@ucsd.edu, 858 534-6184

Schedule

• Lectures: 2:00-2:50PM, W, Center 212
• Discussion: 3:00-3:50PM, W, Center 212

Textbook

• Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, 2007
• Altera DE1 Education Kit
• Teaching Assistants

• Thomas Weng, E-mail: thomaslw (at) gmail
• Renshen Wang, E-mail: rewang@cs
• Chengmo Yang, E-mail: c5yang@cs
• Mingjing Chen, E-mail: mjchen@cs
• Office Hours:
  Check the CSE140 page for the CSE140 TA office hours.
• Lab hours: please check webboard for details 

WebBoard for CSE140/L
Your webboard account is your UCSD account and your PID is your password.

• http://webboard.ucsd.edu

Lecture Notes

• Lecture 1: Introduction
  
• Lecture 3: Discussion on Combinational Logic
  
• Lecture 4: Sequential Networks, Devices, Shifters, and Counters
  
• Lecture 5: Sequential Networks, Counters
  
• A guide to debouncing,
  Lecture 6: Sequential Network Interface and State Assignement
  
• Lecture 7: Transform of Mealy and Moore Machines
  
• Lecture 8: System Design
  
• Lecture 9: Hardware Description Languages
  

Discussion notes

• Discussion notes

Labs (68%)

• Report and demonstration guidelines
• Additional resources
• Careful operations on the boards are recommended, since we have burnt DE2 boards for unknown reasons. Do NOT touch the back of a board when it is on power. Always put the board on desk before connecting the power line.
  
• There will be 4 labs (computer simulations, board demonstration, report write-up).
  Work in a group of two. One report per group.
  
  • 1. Combinational Circuit Designs: Lab 1 Assignment
  • 2. The Specification and Usage of Flip-Flops Lab 2 Assignment
  • 3. Finite State Machines Lab 3 Assignment (Due postponed to Friday 5/22)
  • 4. System Design using Datapath and Control Subsystems Lab 4 Assignment
    New: Lab slides up - Lab slides and Cpu demo
    
    

Exercise

Exercise, 6/2/09

Exercise solution

Office hours before final (Embedded system lab)

Wed 6/10 5:00-6:30PM.

Thu 6/11 12:30-2:00PM.

Final (30%)

3:00-4:30PM F 6/12.