 | 
Institute Affiliation:
Contact Information:
Phone:
858-534-6181
Email:
tullsen@cs.ucsd.edu
Personal Home Page
| | Dean M. Tullsen - Assistant Professor
Processor architecture for high-end computing; widely credited with an innovation that can double the performance of a new generation of microprocessors.
Professor Tullsen's work on simultaneous multi-threading (SMT), a way to allow microchips to process twice as many instructions in the same amount of time in exchange for a 5% increase in hardware cost, led to adoption of this innovation by Intel (which dubbed it "hyper-threading") starting with a line of Xeon server chips in 2002. While initially used in high-performance processing, SMT will gradually be built into desktop PCs by Intel and eventually other manufacturers. Tullsen is currently working on SMT-related improvements, including operating systems and compilers, as well as working to define the next generation of processor architectures beyond SMT. Tullsen is also currently doing research on improvements in microprocessor power consumption, and is an originator of the concept of Critical Path Prediction (CPP), a way to optimize and speed processing by determing the fraction of executed instructions in a program that are most critical--and providing those instructions with privileged access to critical resources.
Capsule Bio:
Dean M. Tullsen joined the UCSD faculty in 1996, after receiving his PhD from the University of Washington. Between getting his M.S. from UCLA and going to Washington, he spent four years as a computer architect at AT&T Computer Systems/AT&T Bell Labs, and a year teaching in China. He has received an NSF Career Award and a Charles Lee Powell faculty fellowship, and currently is a PI on two $300K+ grants from the NSF, and one from the Semiconductor Research Corporation. With Brad Calder, he co-directs the Processor Architecture and Compilation Lab at UCSD. He holds three patents for simultaneous multi-threading.
| |
