Speaker: Krste Asanovic
Massachusetts Institute of Technology

Monday, October 17, 2005
11:00 a.m.
EBU3B 1202

ABSTRACT

Complex, high-performance, low-power information processing systems usually incorporate a mixture of hardware and software elements, and pose significant design and implementation challenges. Conventional register-transfer level (RTL) hardware design is too low-level, requiring designs to be partitioned into collections of combinational gates separated by clocked registers. Conversely, threaded parallel software design is too high-level, and difficult to synthesize to efficient gate-level implementations. In this talk, we'll describe initial work at MIT on the Unit-Transaction Level (UTL) model, which represents a design as a network of "transactor" (transactional actor) units connected by decoupled message queues. UTL provides a natural level of design representation that supports both hardware and software components, and which allows efficient hardware implementations that sidestep many of the difficult physical issues inherent in mapping RTL designs.

The RAMP (Research Accelerator for Multiprocessors) project is a multi-University collaboration to develop an FPGA-based multiprocessor emulation platform, which will allow experimental kiloprocessor systems to run applications at high speed. We believe this platform will revolutionize computer architecture research both by increasing the fidelity of system models, and by encouraging software developers to explore new architectural ideas. We will give an overview of the RAMP project goals and describe the RAMP design framework, which uses the UTL design discipline to manage mapping of multiprocessor designs onto the emulation hardware.

BIO

Krste Asanovic is an Associate Professor in the MIT Department of Electrical Engineering and Computer Science, and a member of the MIT Computer Science and Artificial Intelligence Laboratory. He received a B.A. in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from UC Berkeley in 1998. His primary research interests are computer architecture and VLSI design.