Conference papers:

 

 

1

L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, C. K Cheng,

High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication.

To appear in Proceedings of IEEE ASP-DAC, 2009. (PDF)

 

 

 

 

2

Y. Zhang, L. Zhang, A. Deutsch, G. A. Katopis, D. M. Dreps, E. Kuh, C. K Cheng,

On-chip Bus Signaling Using Passive Compensation.

To appear in Proceedings of IEEE EPEP, 2008. (PDF)

 

 

 

 

3

Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, C. K Cheng,

On-chip High Performance Signaling Using Passive Compensation.

To appear in Proceedings of IEEE ICCD, 2008. (PDF)

 

 

 

 

4

L. Zhang, W. Yu, Y. Zhang, R. Wang, A. Deutsch, G. A. Katopis, D. M. Dreps, J. Buckwalter, E. Kuh, C. K Cheng,

Low Power Passive Equalization Design for Computer Memory Links.

In: Proceedings of IEEE Symposium on High-Performance Interconnects, 2008. (PDF)

 

 

 

 

5

L. Zhang, W. Yu, H. Zhu, A. Deutsch, G. A. Katopis, D. M. Dreps, E. Kuh, C. K Cheng,

Low Power Passive Equalizer Optimization Using Tritonic Step Response.

In: Proceedings of IEEE/ACM DAC, 2008. (PDF)

 

 

 

 

6

L. Zhang, W. Yu, H. Zhu, C. K Cheng,

Clock Skew Analysis via Vector Fitting in Frequency Domain.

In: Proceedings of IEEE ISQED, 2008. (PDF)

 

 

 

 

7

L. Zhang, H. Zhu, J. Liu, C. K Cheng,

High Performance Current-Mode Differential Logic.

In: Proceedings of IEEE/ACM ASP-DAC, 2008. (PDF)

 

 

 

 

8

W. Zhang, Y. Zhu, W. Yu, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, C. K Cheng,

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.

In: Proceedings of IEEE DATE, 2008. (PDF)

 

 

 

 

9

L. Zhang, H. Chen, B. Yao, K. Hamilton, C. K Cheng,

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. In: Proceedings of IEEE ISQED, 2007. (PDF)

 

 

 

 

10

W. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, C. K Cheng,

Fast Power Network Analysis with Multiple Clock Domains.

In: Proceedings of IEEE ICCD, 2007 (PDF)

 

 

 

 

11

T. Jing, L. Zhang, J. Liang, J. Xu, X. Hong, J. Xiong, L. He,

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.

In: Proceedings of IEEE/ACM ASP-DAC, 2005. (PDF)

 

 

 

 

12

L. Zhang, T. Jing, X. Hong, J. Xu, J. Xiong, L. He.

Performance and RLC Crosstalk Driven Global Routing.

In: Proceedings of IEEE ISCAS, 2004. (PDF)

 

 

 

 

13

L. Zhang, T. Jing, X. Hong, J. Xu, L. He, J. Xiong.

Performance Optimization Global Routing with RLC Crosstalk Constraints.

In: Proceedings of IEEE ASICON, 2003. Outstanding student paper award (PDF)

 

 

 

 

Journal papers:

 

 

1

L.Zhang, W. Yu, Y. Zhang, R. Wang, A. Deutsch, G. A. Katopis, D. M. Dreps, J. Buckwalter, E. Kuh, C. K. Cheng, Analysis and Optimization of Low Power Passive Equalizers for CPU-Memory Links. Submitted to: IEEE Transactions on Advanced Packaging.

 

 

 

 

2

L. Zhang, T. Jing, X. Hong, J. Xu, J. Xiong, L. He. CEE-Gr: A Global Router with Performance Optimization under Multi-Constraints. Chinese Journal of Semiconductors, 2004. (PDF)

 

 

 

 

3

L. Zhang, T. Jing, X. Hong, C. Yang, M. Shen. GUI Design Based on Registration Mechanism for Data-Path Layout. Computer Engineering and Applications, 2003. (PDF)