[Michael Taylor]
      Michael B. Taylor

      Assistant Professor
      Computer Science and Engineering
      University of California, San Diego
                                                              

          email
       EBU 3b 4110                 office
      +1 (858) 822 2924          phone
      +1 (858) 534 7029          fax


I am an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego. I received a PhD and an SM in Electrical Engineering and Computer Science from MIT. I was a rebellious undergraduate in the Dartmouth College CS department.


Broader Interests: Novel Systems
My general interests center around the design, construction, and analysis of novel hardware and software systems.


Current Research

I direct the Laboratory for Effective Parallelism, which encompasses my group's ongoing projects, including:
Teaching
Fall 2008 CSE 141: Introduction to Computer Architecture
Fall 2008 CSE 141L: Design and Implement Your Own Processor
Spring 2008 CSE 141: Introduction to Computer Architecture
Spring 2008 CSE 141L: Design and Implement Your Own Processor
Winter 2008 CSE 240B: Advanced/Parallel Computer Architecture
Fall 2007 CSE 291: Design of Concurrent VLSI Architectures
Spring 2007 CSE 141: Introduction to Computer Architecture
Spring 2007 CSE 141L: Design and Implement Your Own Processor
Fall 2006 CSE 240A: Principles of Computer Architecture
Spring 2006 CSE 240B: Advanced Graduate Computer Architecture

I am the coach for the UCSD ACM Programming Team and arranged (along with help from Michael Vrable and many others) the UCSD 2007 Fall Programming Contest.

This year, the UCSD ACM Team placed 2nd out of a field of 63 teams which included schools like CalTech, Harvey Mudd, USC, UCLA, UCSB, UNLV, and UCI. UCSD was the only school to have two teams place in the top five.

I also arranged (along with help from many others) the UCSD 2006 Fall Programming Contest and coached the 2006 ACM Team, which placed 6th out of 74 teams.


Previous Research
As one of the lead students in the MIT Raw project, I led the design and implementation of the Raw microprocessor, which targeted the leading VLSI technology of the time. I also contributed heavily to almost all of the software systems that we built to support the microprocessor.

The purpose of Raw was to demonstrate architectural solutions to scalability problems in modern day microprocessors. The Raw architecture exposes the transistor resources of VLSI chips through the tile abstraction, the pin resources through the I/O port abstraction, and the wiring resources through on-chip networks.

Because the Raw architecture exposed the on-chip resources more effectively than existing sequential architectures (for instance the P6 micro-architecture, the basis of the Pentium-M), Raw was able to outperform Intel desktop processors, implemented with better process technology, across a variety of applications.

One of the key ideas that came out of the Raw research was the formulation of the Scalar Operand Network (SON), a unique class of sub-nanosecond network responsible for routing operands between functional units and memories in a distributed microprocessor. Communication between two instructions on different tiles via SON is shown on the lower-right.

My team implemented the 16-tile Raw microprocessor, shown to the upper-left, in IBM's SA-27E 180 nm 6-layer Cu ASIC process. The 18.2 mm x 18.2 mm chip was, at least at the time, the largest design that the IBM ASIC division had targeted for SA-27E. Each tile contains computing power equivalent to a single-issue pipelined processor. We taped out the chip in August '02, and received prototypes back in late October '02. The motherboard was assembled January '03. A supercomputer prototype with 64 Raw chips (1024-issue) is being constructed.

More pictures are available here.


Collaborations
My collaborators here at UCSD include Steven Swanson, Dean Tullsen, Yoav Freund, CK Cheng, and the members of Calit2.



Downloads

Selected Publications
        Energy and Switch Area Optimizations for FPGA Global Routing Architectures
        Yi Zhu, Yuanfang Hu, Michael Taylor, and Chunk-Kuan Cheng
        ACM Transactions on Design Automation of Electronic Systems, Accepted July 2008.

        Advancing Supercomputer Performance Through Interconnection Topology Synthesis.
        Yi Zhu, Michael Taylor, Scott B. Baden and Chunk-Kuan Cheng
        International Conference on Computer-Aided Design, 2008.

        Tiled Multicore Processors.
        M. Taylor, et al.
        in Multicore Processors and Systems
        edited by Steve Keckler, Kunle Olukotun, and Peter Hofstee. To appear, Springer, 2008.

        Tiled Microprocessors.
        Michael Bedford Taylor
        PhD Thesis, Massachusetts Institute of Technology, February 2007.

        FPGA Global Routing Architecture Optimization Using a Multicommodity Flow Approach.
        Y. Hu, Y. Zhu, M.B. Taylor, and C.K. Cheng.
        IEEE Int. Conf. on Computer Design, pp. 144-151, 2007.

        Stream Multicore Processors.
        Michael Bedford Taylor, Walter Lee, Jason Eric Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Rodric Rabbah, Saman Amarasinghe, and Anant Agarwal.
        In Processor Design: System-on-chip Computing for ASICs and FPGAs (hardcover)
        Edited by Jari Nurmi (Editor)         2007.

        Runtime checking for program verification.
        Karen Zee, Viktor Kuncak, Michael Taylor, and Martin Rinard.
        7th International Workshop, RV 2007, Vancover, Canada, March 13, 2007, Revised Selected Papers.
        Lecture Notes on Computer Science, Springer Berlin, vol. 4839/2007, p. 202-213.

        Scalar Operand Networks,
        by Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
        MIT/LCS Technical Memo LCS-TM-644, April 2004.
        IEEE Transactions on Parallel and Distributed Systems (Special Issue on On-chip Networks), February 2005. (pdf) (Appendix pdf)

        Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,
        by Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
        Proceedings of the International Symposium on Computer Architecture, June 2004. (pdf)

        Scalar Operand Networks:
        On-chip Interconnect for ILP in Partitioned Architectures        ,
        by Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
        Proceedings of the International Symposium on High Performance Computer Architecture, February 2003. (pdf)  

        A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,
        by Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Walter Lee, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Saman Amarasinghe, and Anant Agarwal.
        Proceedings of the IEEE International Solid-State Circuits Conference, February 2003. (pdf)

        The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,
        by Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe and Anant Agarwal.
        IEEE Micro, March/April 2002. (pdf)

        Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,
        by Jason Sungtae Kim, Michael Bedford Taylor, Jason Miller, and David Wentzlaff.
        International Symposium on Low Power Electronics and Design, August 2003.  (pdf)
         
        Design Decisions in the Implementation of a Raw Architecture Workstation,
        by Michael Bedford Taylor.
        MS Thesis, Cambridge, MA, September, 1999. (pdf)

        The Raw Specification
        by Michael Bedford Taylor.
        Final Version (5.02). December 2005. (pdf)

        Baring it all to Software: Raw Machines,
        by Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal.
        IEEE Computer, September 1997, pp. 86-93.  (pdf)
         
        The RAW Benchmark Suite: Computation Structures for General Purpose Computing,
        by Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Srikrishna Devabhaktuni, and Anant Agarwal.
        IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 1997.  (pdf)
         

        ... More publications ...


Workshops & Talks
        Scalar Operand Networks for Tiled Microprocessors,
        2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN) (google video)
        Stanford, CA. December 2006.

        Prototyping Raw,
        International Symposium on Computer Architecture, Workshop on Architectural Research Prototyping (WARP)
        Boston, MA. June 2006.

        Evaluating the Raw Microprocessor: Scalability and Versatility,
        International Symposium on Computer Architecture.
        Munich, Germany. June 21, 2004.

        Evaluating the Raw Microprocessor,
        Boston Area Computer Architecture Workshop.
        Boston, MA. January 30, 2004.

        Scalar Operand Networks,
        International Symposium on High Performance Computer Architecture.
        Anaheim, California. February 12, 2003.

        A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,
        IEEE International Solid-State Circuits Conference.
        San Francisco, California. February 11, 2003. (pdf)   (powerpoint with some transcript)

        Panel Chair,
        2nd MIT Computer Architecture Workshop,
        Gloucester, Massachusetts. September 9, 2002.

        The Raw Microprocessor - Exposing Chip Resources to Software,
        Symposium on Hardware/Software Interfacing for Performance Enhancements.
        St Cloud, Minnesota. April 26, 2002.

        The Raw Processor - A Scalable 32-bit Fabric for Embedded and General Purpose Computing,
        Hotchips XIII.
        Palo Alto, California. August 21, 2001. (pdf , powerpoint with transcript)
         

Technology Policy Advocacy
Software
        A tool for deionization, which enables application embedding and improved benchmark precision.


Miscellaneous
Mailing Address

            

       Prof. Michael B. Taylor
      Dept. of Computer Science and Engineering
      University of California, San Diego
      9500 Gilman Drive EBU 3b-4110 MC 0404
      La Jolla, CA 92093-0404