Research interests:

 

 

 

-- Clock network distribution (tree, tree+links, mesh, etc.), clock skew analysis

 

 

-- High speed on-chip/off-chip interconnect design

 

 

-- Interconnect equalization, low power design

 

 

-- Routing and placement algorithm

 

 

 

 

Research experience:

 

 

 

-- Internship, clock synthesis group in Synopsys, Inc, Mountain View, San Jose, Jun. 2006-Sept. 2006

-- Clock mesh synthesis and distribution algorithm development.

 

 

 

 

 

-- Internship, EDA Lab in NEC Corporation, Kawasaki, Japan, Jun. 2005-Aug. 2005

-- Clock planning system and link insertion algorithms development considering process variations

 

 

 

 

 

-- Research assistant, CSE Dept. University of California, San Diego, Sept. 2004-present

 

 

-- On-chip and off-chip interconnect analysis and optimization,

-- Clock network analysis, clock distribution

-- Current mode differential logic design and analysis

 

 

 

 

 

-- Research assistant, EDA Lab in CSE Dept. Tsinghua Univ., Beijing, China, Sept. 2002-Jul. 2004

-- Standard cell global routing algorithms

-- Crosstalk estimation and reduction in global routing

 

 

 

 

 

-- Research assistant, CAD Lab in the Institute of Microelectronics, Tsinghua University, Beijing, China, Jun. 2001-Jun. 2002

-- Development of a computer aided manufacture software for silicon wafer manufacture

 

 

 

 

 

-- Research assistant, IC Design Lab in the Institute of Microelectronics, Tsinghua University, Beijing, China, Jul. 2000-Sept. 2001

 

 

-- Logic design, logic verification, circuit simulation, layout design, and post simulation of a Serial Code Generator circuit

 

 

 

 

Publication