CSE 140 Components and Design Techniques for Digital Systems Spring 2009

University of California, San Diego

Course Information

• Objective of this course is to introduce digital components and digital systems designs.

Instructor

• CK Cheng, CSE2130, ckcheng+140@ucsd.edu, 858 534-6184

Schedule

• Outlines (Use index to check the location of the textbook)
• Lectures: 2:00-3:20PM TTH, Center 216.
• Discussion: 2:00-2:50PM M, Center 212.
• Office hours: 10:30-11:30AM TTH, CSE 2130.
• Office hours: 10:30-11:30AM F6/5, W6/10, F6/12, CSE 2130.

Teaching Assistants

• Thomas Weng, E-mail: thomaslw@gmail.com
• Renshen Wang, E-mail: rewang@cs.ucsd.edu
• Chengmo Yang, E-mail: c5yang@cs.ucsd.edu
• Mingjing Chen, E-mail: mjchen@cs.ucsd.edu
• Office Hours: Mon 3:00-4:30PM and Wed 4:30-6:00PM   (Mingjing)
•                    Tue 12:30-2:00PM and Thu 12:30-2:00PM  (Chengmo)
•                    CSE(EBU3B) B250A
  
  
• Review section for midterm 2: 05/12/09 Tu 07:00 P -- 07:50 P CENTR 216

WebBoard for CSE140/L

• http://webboard.ucsd.edu

Textbook

• Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, 2007

Lecture Notes and Exercises

• Lecture 1: Introduction
  
• Lecture 2: Combinational Logic, Boolean Algebra
  
• Exercise 1: 2.1, 2.2, 2.5, 2.9, 2.11, 2.13.
• Lecture 3: Combinational Logic, K-Map I
  
• Lecture 4: Combinational Logic, K-Map II
• Discussion section 4/6
• Discussion section 4/13
  
• Lecture 5: Combinational Logic, K-Map III
• Lecture 6: Combinational Logic, Quine-McCluskey Approach
• Lecture 7: Combinational Logic, Other Types of Gates
• More exercises on cominational logic, April 16, 2009  (Solutions)
• Lecture 8: Sequential Networks, Memory Devices
• Discussion section 4/20
• Lecture 9: Sequential Networks, Specification
• Lecture 10: Sequential Networks, Implementation
• Lecture 11: Sequential Networks, Timing
• Exercise 2: 3.4, 3.7, 3.8, 3.13, 3.23, 3.24, 3.26, 3.27, 3.28, 3.29, 3.30.
• Midterm 1 Solutions
• Lecture 12: Combinational Standard Modules: Decoder, Encorder
• Lecture 13: Combinational Standard Modules: Mux, DeMux, Shifters
• Exercise 3: 2.25, 2.26, 2.27, 2.29, 2.30, 2.31, 2.35
• Exercise 4: Sequential Networks and Standard Modules
• Exercise 4 solution
• Discussion section 5/4
• Discussion section 5/11
  
• Lecture 14: Combinational Standard Modules: Adders, Multipliers
• Lecture 15: System Designs I
• Lecture 16: System Designs II
• Lecture 17: System Designs III
• Lecture 18: Sequential Modules
• Lecture 19: Standard Sequential Modules
• Exercise 5: 5.1, 5.2, 5.3, 5.5, 5.6
• Exercise 6
• Midterm 2 Solutions
• Discussion section 6/1 (exercise 6 solutions)
• Final exercise solution

Annoucement for JSOE and Local Companies

• JSOE TIP is calling for students with FPGA experience, several great projects in summer 2009 need high caliber interns, contact Michelle Vavra, mvavra@soe.ucsd.edu, 822-6772, e.g. Sample from OKSI

Grading

• Midterm 1: 25% (T 4/21)
• Midterm 2: 30% (TH 5/14)
• The better of the two midterm scores is counted.
• Final Exam: 40% (3:00-6:00PM, Tu 6/9)